Integrated circuits frequently utilize planarized or smoothed dielectric layers. Planarized or smoothed dielectric layers facilitate the subsequent formation of overlying reliable conductive runners.
One planarization or smoothing process is depicted in FIGS. 1-5. In FIG. 1, substrate 11 denotes a substrate which may illustratively be a dielectric or an oxide of silicon. In general, the term "substrate" means a layer which lies beneath or supports other layers. Reference numerals 13 and 15 denote conductive runners which may contain substantial amounts of aluminum, tungsten, copper, etc. Reference numeral 17 denotes a dielectric, illustratively containing predominantly an oxide of silicon formed from a chemical precursor. Dielectric 17 is somewhat conformal and exhibits a recess 19 between (and slightly above) runners 13 and 15.
FIGS. 2-5 illustrate one method for smoothing or planarizing dielectric 17 in the vicinity of recess 19. In FIG. 2, a photoresist 21 is deposited and patterned using conventional sharp focus. After the photoresist has been developed, unwanted resist is washed away and a portion of the photoresist 21 remains above recess 19.
Next, the wafer is inspected with SEM (scanning electron microscope) apparatus to ensure that recesses 19 are fully covered and then (using either an optical microscope or overlay machine) that photoresist 21 is reasonably aligned with recess 19. Typically, it is also necessary to measure the dimensions of photoresist 21 with a SEM.
Next, in FIG. 3, photoresist 21 is formed by heating it to a temperature of approximately 150.degree. C. for a period of time of approximately 1 minute, followed by a second heating step at approximately 225.degree. C. for approximately 1 minute.
In FIG. 4, an additional new blanket layer of photoresist 23 is then applied.
Next, an etching process is performed. The etching process etchs photoresist 21 and 23 at approximately the same rate as dielectric 17. FIG. 5 schematically illustrates the portion of the wafer after the etching process has been completed. Recess 19 has been at least partially eliminated (although a small recess 25 may still remain). Generally the upper surface 27 of dielectric 17 is smoother or more planar than the upper surface 31 of dielectric 17 in FIG. 1.
The above process, is somewhat long and cumbersome, requires two photoresist applications, and a heating step which impacts the thermal budget. Those concerned with the development of integrated circuit fabrication have consistently sought better methods of planarization.